1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device that selects any one of a plurality of selection lines based on an address signal.
2. Description of Related Art
A semiconductor memory device, typified by a dynamic random access memory (DRAM), includes a large number of word lines for selecting memory cells. To select any one of the word lines, a row address constituted of a plurality of bits needs to be decoded.
With the recent growth in storage capacity, however, the number of bits of a row address has become more than ten. Decoding such a row address at a time not only needs an extremely large number of elements for the decoder but also lowers the decoding speed. Upper bits of the row address are therefore typically predecoded to select any one of memory mats, and lower bits of the row address are predecoded to select a word line included in the selected memory mat (see Japanese Patent Application Laid-Open No. 2003-187578). This can reduce the number of elements needed for the decoder and increase the decoding speed.
Depending on the configuration, however, the memory mats may not be able to be selected by predecoding only the upper bits of the row address, and there is a case where most of the bits constituting the row address may need to be predecoded. In such a case, there has been a problem that the number of elements needed for the predecoder becomes extremely large with a drop in the decoding speed.
Such a problem is not limited to circuits for selecting word lines and can also occur in circuits for selecting other selection lines such as column selection lines. The problem is not limited to semiconductor memory devices such as a DRAM, either, and can occur in semiconductor devices in general that include a plurality of selection lines.